Implementation of Multiplierless High-Speed Low Power Split Radix SDF FFT using NEDA Algorithm for Speech Enhancement

Implementation of Multiplierless HighSpeed Low Power Split Radix SDF FFT using NEDA Algorithm for Speech Enhancement
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© 2021 by IJETT Journal
Volume-69 Issue-12
Year of Publication : 2021
Authors : Mr.C.Ramesh Kumar, Dr.M.P.Chitra
DOI :  10.14445/22315381/IJETT-V69I12P209

How to Cite?

Mr.C.Ramesh Kumar, Dr.M.P.Chitra, "Implementation of Multiplierless HighSpeed Low Power Split Radix SDF FFT using NEDA Algorithm for Speech Enhancement," International Journal of Engineering Trends and Technology, vol. 69, no. 12, pp. 66-73, 2021. Crossref, https://doi.org/10.14445/22315381/IJETT-V69I12P209

Abstract
The Split Radix FFT processor is primarily used for low-power FFT processors. It necessitates fewer mathematical operations. FFT, in the traditional sense, demands greater power and area. However, the proposed SDF SRFFT approach uses less power, is faster, and has a shorter delay. In addition, the twiddle factor multiplication in this SRFFT is performed using the New Distributed Arithmetic (NEDA) technique, which lowers the chip area. The SRFFT implementation is designed with the XILINX ISE Tool and implemented on FPGA Spartan6. For various types of acoustic noise, the SNR is improved. Python3 is used to lower voice noise using the suggested SRFFT architecture.

Keywords
Fast Fourier Transform, Butter Fly Unit, Processing Element, Single Delay Feedback, New Distributed Arithmetic, Distributed Arithmetic.

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