Design and Implementation of Effective Elliptic Curve Cryptography Accelerator using Hardware/Software Co-Design on Zynq Board

Design and Implementation of Effective Elliptic Curve Cryptography Accelerator using Hardware/Software Co-Design on Zynq Board
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© 2022 by IJETT Journal
Volume-70 Issue-8
Year of Publication : 2022
Authors : Kirit V. Patel, Mihir V. Shah, Pankaj P. Prajapati, Anil J. Kshatriya
DOI : 10.14445/22315381/IJETT-V70I8P234

How to Cite?

Kirit V. Patel, Mihir V. Shah, Pankaj P. Prajapati, Anil J. Kshatriya, "Design and Implementation of Effective Elliptic Curve Cryptography Accelerator using Hardware/Software Co-Design on Zynq Board," International Journal of Engineering Trends and Technology, vol. 70, no. 8, pp. 327-335, 2022. Crossref, https://doi.org/10.14445/22315381/IJETT-V70I8P234

Abstract
Today, billions of transactions share confidential information in the digital world of IoT (Internet of Things). The security of sharing confidential information has become a crucial issue in the open-ended network. ECC provides the best solution for higher security with less utilization of resources, and now ECC has become the worldwide acceptable solution for confidential data sharing. To achieve the best trade-off between scalability, flexibility, area consumption, and timing execution with main attention to achieve the best performance. The point addition and double point instructions for Point multiplication calculation in the Montgomery algorithm have been restructured to reduce the required clock cycles. This paper presents the design of an area and speed-improved Elliptic Curve Cryptography (ECC) co-processor accelerator with excellent performance. It is implemented on Zynq board 7000, which allows the hardware-software co-design. The simulation is carried out on the Xilinx Vivado platform. The accelerator can relieve the main processor of cryptography tasks, allowing the SoC to share confidential information on the Internet safely. The suggested cryptographic co-processor outperforms other hardware implementations.

Keywords
Field Programmable Gate Array, Galois Field (GF), Elliptic Curve Scalar Multiplication, National Institute of Standards and Technology, HW/SW- Hardware-Software, SoC (System On Chip).

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