Design and Development of Microarchitecture for Dynamic IoT Communication

Design and Development of Microarchitecture for Dynamic IoT Communication
  IJETT-book-cover           
  
© 2021 by IJETT Journal
Volume-69 Issue-11
Year of Publication : 2021
Authors : Nitesh Gaikwad, Dr. Shiyamala. S
DOI :  10.14445/22315381/IJETT-V69I11P201

How to Cite?

Nitesh Gaikwad, Dr. Shiyamala. S, "Design and Development of Microarchitecture for Dynamic IoT Communication," International Journal of Engineering Trends and Technology, vol. 69, no. 11, pp. 1-8, 2021. Crossref, https://doi.org/10.14445/22315381/IJETT-V69I11P201

Abstract
Nowadays, microarchitecture has utilized many digital applications to enrich the performance of the gadget. The microarchitecture is effectively applicable in the Internet of Things (IoT) to maximize communication performance by designing a specific processor. Usually, the microarchitecture in IoT is structured in a dynamic environment to handle the multiple diverse works simultaneously. But the damaged or weak processor can push the process of microarchitecture into trouble by consuming more energy. So, the awareness of microarchitecture merits and limitations is the needed assessment to select a good processor. Hence, this current article has prepared a detailed review of energy efficiency microarchitecture in IoT gadgets and their functions to accelerate communication. Several literature works were discussed with their advances and limitations in both table and graphical way. Finally, the discussion section has elaborated on the common defeats in the reviewed literature and its reason. Finally, future works have directed the following studies to improve the microarchitecture efficiency score.

Keywords
Internet of Things, microarchitecture, dynamic communication, frequency, processor

Reference
[1] Wang, Xi?Xi, et al., Assembling nano–microarchitecture for electromagnetic absorbers and smart devices., Advanced Materials 32(36) (2020) 2002112.
[2] Whittier, D. E., et al., Guidelines for the assessment of bone density and microarchitecture in vivo using high-resolution peripheral quantitative computed tomography., Osteoporosis International 31 (2020) 1607-1627.
[3] Piccoli, Alessandra, et al., Sclerostin regulation, microarchitecture, and advanced glycation end?products in the bone of elderly women with type 2 diabetes., Journal of Bone and Mineral Research 35(12) (2020) 2415-2422.
[4] Whittier, Danielle E., et al., Sex?and site?specific reference data for bone microarchitecture in adults measured using secondgeneration HR?pQCT., Journal of Bone and Mineral Research 35(11 ) (2020) 2151-2158.
[5] Pecci, Raffaella, et al., 3D printed scaffolds with random microarchitecture for bone tissue engineering applications: Manufacturing and characterization., Journal of the mechanical behavior of biomedical materials 103 (2020) 103583.
[6] Han, Xuequan, et al., Association between knee alignment, osteoarthritis disease severity, and subchondral trabecular bone microarchitecture in patients with knee osteoarthritis: a cross-sectional study., Arthritis Research & Therapy 22(1) (2020) 1-11.
[7] Kumar, Chanchal, et al., Post-silicon microarchitecture., IEEE Computer Architecture Letters 19(1) (2020) 26-29.
[8] Shrestha, Rahul., A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications., IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29(1) (2020) 65-75.
[9] Reyes, Karen J. Campoverde, et al. ,Bone density, microarchitecture and strength estimates in white versus African American youth with obesity., Bone 138 (2020) 115514.
[10] Antonov, Alexander, Pavel Kustarev, and Sergey Bikovsky. ,MLIP Cores: Designing Hardware Generators with Programmable Microarchitectural Mechanisms., 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, (2020).
[11] Sepúlveda, Johanna., Secure Cryptography Integration: NoC-Based Microarchitectural Attacks and Countermeasures., Network-on-Chip Security and Privacy (2021) 153.
[12] Wang, Lei, et al., Wpc: Whole-picture workload characterization across intermediate representation, isa, and microarchitecture., IEEE Computer Architecture Letters (2021).
[13] Mao, Yuxiao, Vincent Migliore, and Vincent Nicomette. ,REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection., 2020 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW). IEEE, (2020).
[14] Antonov, Alexander, Pavel Kustarev, and Sergey Bikovsky. ,MLIP Cores: Designing Hardware Generators with Programmable Microarchitectural Mechanisms., 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, (2020).
[15] G?itan, VasileGheorghi??, and IonelZagan., An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications., Sensors 21(13) (2021) 4500.
[16] Shashidhara, H. R., et al., Design and Implementation of Argo NI-NoC Micro-architecture for MPSoC Using GALS Architecture., Emerging Trends in Electrical, Communications, and Information Technologies. Springer, Singapore, (2020) 451-463.
[17] Semal, Benjamin, et al., A Study on Microarchitectural Covert Channel Vulnerabilities in Infrastructure-as-a-Service., International Conference on Applied Cryptography and Network Security. Springer, Cham, (2020).
[18] Omar, Hamza, Brandon D`Agostino, and Omer Khan. ,OPTIMUS: A security-centric dynamic hardware partitioning scheme for processors that prevent microarchitecture state attacks., IEEE Transactions on Computers 69(11) (2020) 1558-1570.
[19] Antonov, Alexander, and Pavel Kustarev. ,Strategies of Computational Process Synthesis—a System-Level Model of HW/SW (Micro) Architectural Mechanisms., 2020 9th Mediterranean Conference on Embedded Computing (MECO). IEEE, (2020).
[20] Jiao, Qiang, et al. ,Design of a Convolutional Neural Network Instruction Set Based on RISC-V and Its Microarchitecture Implementation., International Conference on Algorithms and Architectures for Parallel Processing. Springer, Cham, (2020).
[21] Deng, Yangdong, et al., Toward real-time ray tracing: A survey on hardware acceleration and microarchitecture techniques., ACM Computing Surveys (CSUR) 50(4) (2017) 1-41.
[22] Murray, Sean, et al. ,The microarchitecture of a real-time robot motion planning accelerator., 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, (2016).
[23] Xu, Siyuan, and Benjamin Carrion Schafer., Approximate reconfigurable hardware accelerator: Adapting the micro-architecture to dynamic workloads., 2017 IEEE International Conference on Computer Design (ICCD). IEEE, (2017).
[24] Chang, H. Y., Narayanan, P., Lewis, S. C., Farinha, N. C., Hosokawa, K., Mackin, C., ... & Burr, G. W., AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed. IBM Journal of Research and Development, 63(6) (2019) 8-1.
[25] Song, Mingcong, et al., Towards efficient microarchitectural design for accelerating unsupervised gan-based deep learning., 2018 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, (2018).
[26] Fairouz, Abbas, et al., Hardware Acceleration of Hash Operations in Modern Microprocessors., IEEE Transactions on Computers (2020).
[27] Guo, Licheng, et al. ,Hardware acceleration of long read pairwise overlapping in genome sequencing: A race between fpga and gpu., 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, (2019).
[28] Smith, James E., and Ashutosh S. Dhodapkar. ,Dynamic microarchitecture adaptation via co-designed virtual machines., 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No. 02CH37315). IEEE, 1 (2002).
[29] Grayson, Brian, et al. ,Evolution of the Samsung Exynos CPU microarchitecture., 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, (2020).
[30] Adegbija, Tosiron, et al. ,Enabling right-provisioned microprocessor architectures for the internet of things., ASME International Mechanical Engineering Congress and Exposition.. American Society of Mechanical Engineers, 57571 ( 2015).
[31] Kiat, Wei-Pau, et al., An energy-efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications., Microprocessors and Microsystems 73 (2020) 102966.
[32] Vitullo, Francesco, et al., Low-complexity link microarchitecture for mesochronous communication in networks-on-chip., IEEE Transactions on Computers 57(9) (2008) 1196-1201.
[33] Kansakar, Prasanna, and Arslan Munir. ,Selecting Microarchitecture Configuration of Processors for Internet of Things., IEEE Transactions on Emerging Topics in Computing 8(4) (2018) 973-985.
[34] Muzaffar, Shahzad, and Ibrahim M. Elfadel., A Domain-Specific Processor Microarchitecture for Energy-Efficient, Dynamic IoT Communication., IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27(9) (2019) 2074-2087.
[35] Adegbija, Tosiron, et al., Microprocessor optimizations for the internet of things: A survey., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37(1) (2017) 7-20.
[36] Cheikh, Abdallah, et al., The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes., International Conference on Applications in Electronics Pervading Industry, Environment and Society. Springer, Cham, (2017).
[37] Soliman, Wasim Ghder, et al., Reconfigurable Microarchitecture-Based PMDC Prototype Development for IoT Edge Computing Utilization., IEEE Sensors Journal 21(2) (2020) 2334-2345.
[38] Chen, Yajing, et al., A low power software-defined-radio baseband processor for the Internet of Things., IEEE international symposium on high-performance computer architecture (HPCA). IEEE, (2016).
[39] Limaye, Ankur, and TosironAdegbija., HERMIT: A benchmark suite for the internet of medical things., IEEE Internet of Things Journal 5.5 (2018) 4212-4222.
[40] Saini, Harpreet Singh, and R. D. Daruwala. ,Human-machine interface in the internet of things system., International conference on computing communication control and automation (ICCUBEA). IEEE, (2016).
[41] Pereira, Pablo Punal, et al. ,Enabling cloud connectivity for mobile internet of things applications., IEEE seventh international symposium on service-oriented system engineering. IEEE, (2013).
[42] Rahmani, Amir-Mohammad, et al. ,Smart e-health gateway: Bringing intelligence to internet-of-things based ubiquitous healthcare systems., 2015 12th Annual IEEE Consumer Communications and Networking Conference (CCNC). IEEE, (2015).
[43] Satapathy, Lalit Mohan, Samir Kumar Bastia, and Nihar Mohanty. ,Arduino based home automation using Internet of things(IoT)., International Journal of Pure and Applied Mathematics 118(17) (2018) 769-778.
[44] Ayadi, Amira, and Salma Sassi. ,Privacy in the age of the internet of things: Challenges and prospects., 2016 Global Summit on Computer & Information Technology (GSCIT). IEEE, (2016).
[45] Maarala, AlttiIlari, Xiang Su, and Jukka Riekki. ,Semantic reasoning for context-aware Internet of Things applications., IEEE Internet of Things Journal 4(2 ) (2016) 461-473.
[46] Liu, Zhiguo, et al. ,Saving energy on processor micro-architecture level for big data stream mobile computing., 2017 IEEE Second International Conference on Data Science in Cyberspace (DSC). IEEE, (2017).
[47] Jain, Saurabh, Longyang Lin, and Massimo Alioto. ,Dynamically adaptable pipeline for energy-efficient microarchitectures under wide voltage scaling., IEEE Journal of Solid-State Circuits 53(2) (2017) 632-641.
[48] Reaz, Mamun Bin Ibne, Md Shabiul Islam, and Mohd S. Sulaiman. ,A single clock cycle MIPS RISC processor design using VHDL., ICONIP`02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No. 02EX575). IEEE, (2002).
[49] Mullins, Robert, Andrew West, and Simon Moore. ,The design and implementation of a low-latency on-chip network., Asia and South Pacific Conference on Design Automation,. IEEE, (2006).
[50] Cavallaro, Joseph R., and Mani Vaya. ,Viturbo: a reconfigurable architecture for Viterbi and turbo decoding., IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings.(ICASSP`03). IEEE, 2 (2003).